The invention relates to communications systems and methods, and, more particularly, to digital communications systems and associated methods over parallel communications channels.
Digital communications are widely used for the transmission of voice, data and video information. Such transmission can extend over large geographical distances, between components within a personal computer, or only between adjacent circuit portions on an integrated circuit. Certain such communications applications benefit from or require the conversion of serial data into parallel data for simultaneous transmission over parallel communications channels, or more generically, from Mxe2x80x2 ary symbols to Nxe2x80x2 ary symbols.
At the receiving end, the parallel data is desirably converted back into the serial data, and with the bits or symbols in the correct order to avoid data errors.
Unfortunately, the demand for greater data transmission volumes and at ever higher speeds, may result in skew at the receiver. In other words, the parallel communications channels may introduce different delays to the parallel symbol strings they carry. Because of skew, the parallel symbol strings at the receiver can then no longer be simply reassembled into the starting data.
The skew problem with parallel communications channels has been addressed in a number of ways. For example, U.S. Pat. No. 4,677,618 to Haas et al. recognized the dispersion introduced by wavelength division multiplexed communications channels over optical fiber. This patent discloses determining the relative delays between the channels based upon detecting two bits in a given byte of data. The relative times of arrival of the remaining bits in a byte are predetermined using the relative delay between the two detected bits and the known frequency-related dispersion characteristics of the transmission medium. Certain bits in each received byte may then be delayed using clock delay lines or registers, thereby accounting for skew.
Along similar lines, U.S. Pat. No. 5,157,530 to Loeb et al. also determines and accounts for skew imparted by dispersion in fiber optic wavelength division multiplexing. Relative delays are used to control adjustable delay devices in each channel.
U.S. Pat. No. 5,408,473 to Hutchinson et al. is directed to a technique for synchronizing run-length-limited data transmitted over parallel communications channels. Block boundary synchronization is established during connection initialization by using a property of a required HALT code to detect block boundaries received in each channel. Skew compensation is effected by comparing the times of detection of the block boundaries in the two channels, and appropriately controlling a variable delay in at least one of the channels. If there is a subsequent loss of synchronization, detected transmission errors will eventually result in connection reinitialization and reestablishment of synchronization. Unfortunately, the transmission of the fixed HALT code to detect boundaries may result in false boundary detection. Moreover, since synchronization is not continuously maintained, the technique may be impractical for higher data rates.
U.S. Pat. No. 5,793,770 to St. John et al. is directed to a high-performance parallel interface (HIPPI) to a synchronous optical network (SONET) gateway, and wherein electronic logic circuitry formats data and overhead signals into a data-frame for transmission over a fiber optic channel. Stripe skew adjustment is based upon SONET framing, and, as such, the circuitry is relatively complicated, comprising as many as 20,000 logic gates, for example.
The difficulty with skew caused by parallel communications channels is also an important issue to be addressed in communications channels between integrated circuit devices. For example, higher transmission speeds increase the sensitivity to skew, as there is a smaller time window to correctly identify a received bit and have it properly align with bits received on the other parallel communications channels. To provide a higher aggregate transmission rate, the number of parallel communications channels can be increased, without increasing the speed of any given communications channel. However, this may result in significant costs for the additional communications channels. Moreover, for communications between integrated circuits, increasing the number of communications channels increases the number of pins needed for connecting the IC. The number of pins and additional packaging complexity may significantly increase the costs of such approaches.
For communications channels between physical layer devices (PLDs) or PHY devices, and logical link devices (LLDs), typical interfaces are asymmetrical and the devices are operated in a push-pull configuration. Because of the asymmetry, relatively expensive memory is required on the PLD since it is polled by the LLD, such as an asynchronous transfer mode (ATM) device. Further developments and improvements in the communications interface between a PLD and LLD are also hampered by the skew difficulty described above as a result of higher bit rates over limited parallel communications channels.
In view of the foregoing background, it is therefore an object of the present invention to provide a communications system and associated methods with simplified and efficient interfaces between a PLD and an LLD.
These and other objects, features and advantages in accordance with the present invention are provided by A communications system comprising a PLD and an LLD, each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the communications system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. In particular, a channel loopback can be initiated in the PLD. Also, the LLD can be provided in two integrated circuit packages to ease pinout requirements.
The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs. The PLD send interface and the LLD send interface are substantially identical, and the PLD receive interface and the LLD receive interface are substantially identical to thereby define the symmetrical interfaces for the communications system. In view of the symmetrical interfaces, the PLD and the LLD may operate in a push-push configuration.
The LLD may comprise, for example, an asynchronous transfer mode (ATM) device. The PLD may comprise one of a synchronous optical network (SONET) device or a synchronous digital hierarchy (SDH) device.
Yet another aspect of the invention is that the pin count of the PLD and LLD may be kept manageable by using higher speed parallel communications channels while accounting for skew. In particular, the PLD send interface may comprise a string-based framing coder for determining and appending a string-based framing code to each information symbol string of information symbol strings to be transmitted in parallel over respective first parallel communications channels, each string-based framing code being based upon at least some of the information symbols in the respective information symbol string. Also, the LLD receive interface may comprise a deskewer for aligning received parallel information symbol strings based upon the string-based framing codes. The information symbols may be binary bits, and the string-based framing codes may be CRC codes, for example.
The deskewer may comprise a framer for framing information symbol strings based upon the respective string-based framing codes, and an aligner for aligning framed information symbol strings relative to one another and based upon the string-based framing codes. The aligner, in turn, may comprise at least one first-in-first-out (FIFO) device connected to the framer for buffering framed information bit strings. The aligner may also include a FIFO controller for aligning framed information bit strings during at least one of a writing and a reading phase of the at least one FIFO device and based upon the string-based framing codes. The string-based coder and deskewing may also be provided for the information signals from the LLD to the PLD.
A method aspect of the invention is for making such a communications system comprising the steps of: providing the PLD with a PLD send interface and a PLD receive interface, providing the LLD with an LLD receive interface to be connected via parallel communications channels to the PLD send interface, and further providing the LLD with an LLD send interface to be connected to the PLD receive interface via parallel communications channels. Moreover, the PLD send interface and the LLD send interface are preferably substantially identical, and the PLD receive interface and the LLD receive interface are preferably substantially identical to thereby define symmetrical interfaces for the system.
In view of the symmetrical interfaces, the PLD and the LLD may operate in a push-push configuration. The LLD may comprise, for example, an asynchronous transfer mode (ATM) device. The PLD may comprise one of a synchronous optical network (SONET) device or a synchronous digital hierarchy (SDH) device.
The method may further comprise the step of providing the PLD send interface with a string-based framing coder for determining and appending a string-based framing code to each information symbol string of information symbol strings to be transmitted in parallel over respective parallel communications channels. Each string-based framing code may be based upon at least some of the information symbols in the respective information symbol string. The method may also comprise the step of providing the LLD receive interface with a deskewer for aligning received parallel information symbol strings based upon the string-based framing codes.
Another aspect of the invention is directed to a method for operating a communications system comprising a physical layer device (PLD) and a logical link layer device (LLD) connected by parallel communications channels. The PLD preferably includes a PLD send interface and a PLD receive interface, and the LLD includes an LLD receive interface connected to the PLD send interface. The LLD may also include an LLD send interface connected to the PLD receive interface. The PLD send interface and the LLD send interface are preferably substantially identical, as are the PLD receive interface and the LLD receive interface. The method of operating the system preferably comprises the step of operating the PLD and the LLD in a push-push configuration.